1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device which detects data by comparing a data current supplied from a memory cell with a reference current supplied from a reference cell.
2. Description of the Related Art
In nonvolatile semiconductor memory devices, memory cells (memory cell transistors) are arranged in an array, and an electric current flows from a selected bit line to a memory cell that is connected to a selectively activated word line. The sensing of this electric current reveals what data is stored in the memory cell, which has been selected both in an X direction and in a Y direction. In such data sensing, generally, an electric current flowing from a selected bit line to a selected memory cell is compared by a sense amplifier with an electric current running through a reference cell that is provided as a reference.
FIG. 1 is a circuit diagram showing the construction of a related-art nonvolatile semiconductor memory device in respect of a portion relevant to data reading. The circuit of FIG. 1 includes a memory cell array 10, a reference cell unit 11, a sense amplifier 13, and gate transistors 14, 15, 16-0, 16-1, 16-2, and 17. The memory cell array 10 includes memory cells (i.e., memory cell transistors) M00 through M02, M10 through M12, M20 through M22, and M30 through M32 arranged in an array. For the sake of convenience of illustration, memory cells are shown as constituting a 3×4 matrix. In actual construction, however, a larger number of memory cells are arranged in an array. A plurality of memory cells arranged in the same row extending in a horizontal direction have gate nodes thereof connected to the same word line. In total, four word lines WL0 through WL3 are provided.
A plurality of memory cells arranged in the same column extending in a vertical direction have drain nodes thereof connected to the same bit line. In total, three bit lines BL0 through BL2 are provided.
The reference cell unit 11 includes reference cells (i.e., reference cell transistors) MR0 and MR1. The reference cell (reference cell transistor) MR0 has a gate node thereof connected to the word line WLR0, and the reference cell (reference cell transistor) MR1 has a gate node thereof connected to the word line WLR1. The drain nodes of the reference cells MR0 and MR1 are connected to a bit line BLR provided for the reference purpose. The transistors of the reference cells have gm (transconductance) that is adjusted to half the size of that of the memory cell transistors. Moreover, source nodes of the memory cells and the reference cells are all fixed to a common potential (array source AS).
When an even-numbered word line WL0 or WL2 is selected in the memory cell array 10, the word line WLR0 is activated in the reference cell unit 11. When an odd-numbered word line WL1 or WL3 is selected in the memory cell array 10, the word line WLR1 is activated in the reference cell unit 11. It should be noted that the memory cells on the upper side of the array source AS are arranged symmetrically with the memory cells on the lower side of the array source AS. With the provision as described above, differences in characteristics are absorbed between memory cells provided on the lower side of the array source AS (i.e., memory cells connected to the even-numbered word line WL0 or WL2) and memory cells provided on the upper side of the array source AS (i.e., memory cells connected to the odd-numbered word line WL1 or WL3).
The sense amplifier 13 is a differential-type amplifier, and is provided with an input terminal DL connected to the memory cell array 10 and an input terminal DLR connected to the reference cell unit 11.
The gate transistors 16-0 through 16-2 together constitute a bit-line selecting gate unit for selecting a bit line, and their gate nodes receive selection signals Y0 through Y2, respectively. As one of the bit-line selection signals Y0 through Y2 is selectively set to HIGH, a corresponding one of the three bit lines BL0 through BL2 is selected. The selected bit line is coupled to the input terminal DL of the sense amplifier 13 through the gate transistor 17.
Moreover, the bit line BLR provided for the reference purpose is coupled to the input terminal DLR of the sense amplifier 13 through the gate transistors 14 and 15. The gate transistors 14 and 15 each have the same characteristics as the gate transistors 16-0 through 16-2, and are provided for the purpose of providing the same load on the electric current path of the memory cell array and on the electric current path of the reference cell unit.
In the following, a description will be given of a basic operation of data reading. For the sake of convenience of explanation, an example to be described here is directed to a system in which an array source is set to the ground, and the two input nodes DL and DLR of the sense amplifier 13 provide respective potentials.
A description will be given of a case in which data “0” stored in the memory cell M10 is read. While the word line WL1 is activated, the gate transistors 16-0 and 17 are made conductive. As a result, the memory cell M10 is coupled to the input terminal DL of the sense amplifier 13. Electric discharge occurs from the input terminal DL to the array source AS through the bit line BL0 and the memory cell M10. The amount of current flowing out of the input terminal DL is referred to as IcelON. IcelON is equal to Icel0, which is the amount of current that runs through a memory cell having data “0” stored therein.
On the reference side, the word line WLR1 is activated to make the gate transistors 14 and 15 conductive. As a result, the reference cell MR1 is coupled to the input terminal DLR of the sense amplifier 13. Electric discharge occurs from the input terminal DLR to the array source AS through the reference bit line BLR and the reference cell MR1. The amount of current flowing out of the input terminal DLR is referred to as Iref. Iref is 0.5Icel0, which is half the amount of Icel0. This is because gm of a reference cell is set to half the size of gm of a memory cell.
Accordingly, respective potentials V(DL) and V(DLR) of the two inputs DL and DLR of the sense amplifier 13 are related as: V(DL)<V(DLR), resulting in the sense amplifier 13 outputting data “0”.
When data “1” is stored in the memory cell M10, on the other hand, the memory cell M10 does not become conductive in response to the activation of the word line WL1. As a result, IcelON that is the amount of an electric current flowing out of the input terminal DL of the sense amplifier 13 is 0, so that V(DL)>V(DLR). This results in the sense amplifier 13 outputting data “1”.
In the nonvolatile semiconductor memory device described above, the sense amplifier 13 may fail to perform proper data sensing because of the presence of capacitance between the bit lines. This will be described in the following.
A case will be examined here in which all the memory cells M00, M32, and M11 store data “1”, and data are retrieved from the memory cells M00, M32, and M11 in the order named.
When the memory cell M00 is read first, no current runs through the memory cell M00 storing data “1”. In this case, the bit line BL0 is charged to a potential responsive to the amount of electric charge supplied from the input terminal DL of the sense amplifier 13. The sense amplifier 13 thus outputs data “1”.
When the memory cell M32 is read next, no current runs through the memory cell M32 storing data “1”. As a result, the bit line BL2 is charged to a potential responsive to the amount of electric charge supplied from the input terminal DL of the sense amplifier 13. The sense amplifier 13 thus outputs data “1”.
When the memory cell M11 is read further, no current runs through the memory cell M32 storing data “1”. It is expected, therefore, that the bit line BL1 is charged to a potential responsive to the amount of electric charge supplied from the input terminal DL of the sense amplifier 13. When this happens, however, the other memory cells M10 and M12 connected to the activated word line WL1 may have data “0” stored therein. In such a case, the bit lines BL0 and BL2 connected to the respective memory cells M10 and M12 are in a charged state by the reading of the memory cells M00 and M32 as described above, and discharge as they are coupled to the array source AS via the respective memory cells M10 and M12. That is, the bit line BL1 that is to be charged and sensed for the reading of data is sandwiched between the bit lines that exhibit an opposite potential change through discharging. As a result, charging of the bit line BL1 is affected by the presence of capacitance between the bit lines, so that the sensing of data by the sense amplifier 13 may fail.
Accordingly, there is a need for a nonvolatile semiconductor memory device in which data sensing is not affected by the presence of capacitance between bit lines.